This invention relates generally to imaging devices, and more particularly, to imaging devices with data converting circuits.
Image sensors are commonly used in electronic devices such as cellular telephones, cameras, and computers to capture images. In a typical arrangement, an electronic device with an image sensor is provided with an array of image sensor pixels arranged in pixel rows and columns.
One type of conventional image sensor features analog-to-digital converter (ADC) circuits each of which is connected to a corresponding column in the image pixel array. The ADC circuits receive signals from image sensor pixels in a selected row via column lines. The ADC circuits may be implemented using a ramp ADC architecture. A ramp ADC may exhibit low power consumption but may require high clock speeds to ensure that the desired frame rate is met.
One way of achieving improved frame rates using the ramp ADC architecture involves dividing the entire ADC range into multiple sub-ranges. A coarse comparison may first be performed to determine in which one of the sub-ranges fine comparison operations should be performed. The coarse comparison determines the most significant bits. Subsequently, fine comparison operations are performed in a selected one of the sub-ranges to determine the remaining least significant bits. This type of data conversion is sometimes referred to as the sub-ranged ramp ADC architecture.
In practice, however, sub-ranged ramp ADCs often suffer from nonlinearity issues such as differential nonlinearity (DNL) when parasitic elements are present. This degraded DNL performance causes the ADC to deviate from its ideal transfer characteristic, resulting in undesired artifacts in the final image. It would therefore be desirable to be able to provide imaging devices having sub-ranged ramp ADCs with improved linearity.